1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having circuits structured by thin film transistors (hereinafter referred to as TFTs). In particular, the present invention relates to a technique of crystallizing a semiconductor film having an amorphous structure.
2. Description of the Related Art
Developments have been advancing recently in forming TFT active layers (indicating semiconductor regions that contain a source and drain region, and a channel formation region) by using semiconductor thin films formed on a substrate having an insulating surface, and applying the TFTs to semiconductor devices having large surface area integrated circuits.
A typical applied example of TFTs, which has been gathering attention, and is referred to as an active matrix liquid crystal display device, has pixel electrodes disposed on a matrix and TFTs applied to switching elements connected to each of the pixel electrodes.
In active matrix liquid crystal display devices, TFTs have been conventionally formed by using amorphous silicon films. However, attempts at manufacturing of TFTs (hereinafter referred to as polysilicon TFTs) which use crystalline silicon films (polysilicon films) in their active layers have been made in order to achieve higher performance. Polysilicon TFTs have high field effect mobility, and therefore it is possible to form circuits having various types of functions.
It is possible to form a pixel portion that performs image display per functional block, and a driver circuit portion for controlling the pixel portion and having shift register circuits, level shifter circuits, buffer circuits, sampling circuits, and the like based on CMOS circuits, on a single substrate for a liquid crystal module mounted in an active matrix liquid crystal display device using polysilicon TFTs.
A technique for manufacturing high quality crystalline silicon films is necessary in order to obtain polysilicon TFTs having good characteristics. Crystallization techniques, which use an excimer laser, are typical and widely known.
On the other hand, a technique disclosed in JP 8-78329 A is another technique for obtaining a crystalline silicon film on a glass substrate. The technique disclosed in JP 8-78329 A is one in which a metallic element for promoting crystallization (typically Ni) is selectively added to an amorphous silicon film, and a crystalline silicon film which spreads out from the metallic element added regions is formed by performing heat treatment. The size of crystal grains obtained is extremely large.
With the aforementioned known technique, it is possible to lower the crystallization temperature of the amorphous silicon film on the order of 50 to 100° C. compared to performing crystallization without using the metallic element. The amount of time necessary for crystallization can also be reduced to {fraction (1/10)} to ⅕ compared to performing crystallization without using the metallic element, so that the technique also allows superior productivity.
Crystalline silicon films obtained by the technique of the aforementioned publication (JP 8-78329 A) have a unique crystal structure in which a multiple number of rod shape crystal aggregates (also referred to as domains) are formed, and all crystals in one crystal aggregate (domain) have the same crystal orientation. The size of the crystal aggregates (domains) is large at from 200 to 300 μm. Further, adjacent crystal aggregates (domains) have different orientations and have a boundary. Electrical characteristics being substantially the same as those of single crystal can be expected to be obtained provided that a channel formation region is formed within one of the crystal aggregates to form TFTs.
However, it is not possible to precisely control the position of the crystal aggregates with conventional techniques, including the technique of the above publication, and it is difficult to form channel formation regions with one crystal aggregate in accordance with the position of each TFT. That is, it is almost impossible to match the positions of the crystal aggregates and the positions of the channel formation regions for all TFTs used in forming the pixel portion and the driver circuit portion.
Crystalline silicon films obtained by the technique of the above publication (JP 8-78329 A) contain a metallic element for promoting crystallization (typically Ni). It is not preferable that a large amount of the metallic element exists within the crystalline silicon film because the metallic element inhibits the reliability and electrical stability of a device using the semiconductor. It is preferable to remove the metallic element quickly after crystallization of the amorphous silicon film, or to reduce its concentration to a level at which it does not exert influence on the electrical characteristics, by using a method referred to as gettering. Further, considering crystal growth mechanisms, a large portion of the metallic elements congregate in the boundaries of the crystal aggregations (domains).
Therefore, although a TFT will have good electrical characteristics if the crystalline silicon film is used for an active layer of the TFT, small differences among various other TFT characteristics will develop, in other words, variations, depending upon whether or not a boundary between adjacent crystal aggregates (crystal aggregates having different orientations) exists, and depending upon the difference in size of the crystal aggregates formed.
Variations will develop in the voltage applied to each pixel electrode if there are variations in the electrical characteristics of the TFTs disposed in the pixel portion, and variations will therefore also develop in the amount of light transmitted. This leads to display irregularities when viewed by observers. The variations are within a permissible range at present and of an order such that there arises no problems. However, pixel size is further made smaller, and the variations will become an extremely large problem for cases in which a very high fineness image is desired.
In the future, channel formation region size (channel length and channel width) is made smaller along with additional reductions in the design rule, and therefore if TFTs are formed having crystal aggregate boundaries in their channel formation regions, a difference will develop in the TFT characteristics (such as mobility, S-value, on current, and off current) compared to TFTs having channel formation regions with no crystal aggregate boundaries. This becomes a cause of a variation in display.
Further, although several experiments for forming crystalline silicon films having uniform grain size at a process temperature equal to or less than the distortion point of glass substrates, that is, at a temperature equal to or less than 600° C., have been proposed, at present a suitable means has not yet been uncovered.
Conventionally it has been difficult to obtain crystalline silicon films having both high uniformity and high mobility. In addition, it is difficult to manufacture at a process temperature equal to or less than 600° C.